=cw4t7abs antiorp at
Fri Oct 23 12:21:23 EDT 1998

>Stephen Handley                         P.O. Box 1443, MS 701
>DSP Multimedia Specialist                       Houston, Texas 77001

                 .Synthesis and optimization of digital circuits, G. DeMicheli,
                    McGraw Hill

                 .The Verilog Hardware Description Language, 2nd Edition, D.
                    Thomas and P. Moorby, Kluwer Academic Publishers

                 .EE487 Lecture note, T. Meng

                 .Digital Integrated Circuits, A design perspective, J. Rabaey,
                    Prentice Hall

                 .Behavioral Compiler Methodology Note, version 3.3a,

                 .A.Hung and T.Meng, "A comparison of fast IDCT algorithm",
                    ACM multimedia systems journals

                 .E.Linzerm and E.Feig, "New scaled DCT algorithm for Fused
                    Multiply/ADD architectures", IBM Research, Yorktown Heights

latency of "reset_loop" = 61 cycles.
latency of "row_loop1" = 31 cycles.
latency of "row_loop2" = 28 cycles.

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