[music-dsp] modelling a spring reverb

[Jon Watte]

> > I wouldn't be so sure. It's fairly typical of today's caches to 
> be able to
> > handle 16-32 cleverly aligned cache lines per time. Given that, plus
> 
> If we were only so lucky. Typical numbers are 4-way and (for 
> really advanced
> cases) 8-way.

Unless by "cleverly aligned" you mean "strided to NOT clash", of 
course. Then the number of data cache lines is:

Pentium 4 L1: 8 kB / 64 bytes == 128

Athlon XP L1: 64 kB / 64 bytes == 1024

Pentium 3 L1: 16 kB / 32 bytes == 512

And a case could be constructed to actually fit that many different 
cache lines in the cache :-)

Cheers,

				/ h+


dupswapdrop -- the music-dsp mailing list and website: subscription info,
FAQ, source code archive, list archive, book reviews, dsp links
http://shoko.calarts.edu/musicdsp/